Real-time buffered image pipeline
Traditionally machine vision cameras are designed that the data rate of the image sensor should match with the frame grabber or PC. But common image data rates will soon exceed 10Gbit/s and move up towards 30Gbit/s over the next years. This means that high performance interface solutions are needed in order to access the full image acquisition potential of these CMOS sensors.
New interface standards arise (like CoaXPress ) to handle these speeds, but they do require high-end frame grabbers and matching PC’s.
Using our buffered image pipeline technology, the data stream from the sensor is decoupled from the datastream on the camera interface. This is done using a new real-time buffered imaging pipeline in the camera. The main advantage is that vision equipment can combine high speed image acquisition with low data rate interfaces (see figure 1).
Figure 1: The image buffer (bucket) receives the image data stream at high speed from the sensor (Step 1 & 2) while outputting the image data at a lower speed to the camera interface ( Step 1 – 5).
Advantages of the buffered imaging pipeline architecture
Throughput improvement at lowest interfacing cost.
Off-load interface, frame grabber and PC requirements for cost optimized system infrastructures with high performance imaging. Use high speed image acquisition (1Gpixel/s @10bit/pixel, or higher) in combination with low cost / low data rate interfaces (like GigE Vision, Camera Link Base)
Gain accuracy at speeds and resolution beyond CCD
shot noise limited imaging: with embedded processing in the camera combining multiple images acquired at high speed improves the signal-to-noise performance in the image. Effectively a lower frame speed results that can be handled by a lower performance interface. see table for example.
Preserve image accuracy
Overcome bit depth limitation (max 8 bit/pixel) in high speed Camera Link configurations by working with Camera Link Base or Medium instead of Camera Link Full.
Buffered pipeline CMOS vs Direct pipeline CMOS & CCD
|Buffered Pipeline CMOS||Direct Pipeline CMOS||Direct Pipeline CCD|
|6x averaging in camera||6x averaging in FG||No averaging|
|Link infrastructure||CL base FG, 1 cable||CL deca FG, 2 cables||CL base FG, 1 cable|
|Bit depth link||10 – 12 bits||8 bits||10 – 12 bits|
|Linear Dynamic Range||Ca. 67-68dB||Limited by 8 bits quantization. (48dB in DN)||ca. 63dB|
|Infrastructure cost savings vs CL-Deca||Saving: up to $1500||–||Saving: up to $1500|
Relevance and application possibilities for vision systems.
Cameras with buffered imaging pipeline architecture offer OEM system manufacturers the following benefits/possibilities in addition to traditional camera architecture solutions:
- Build faster OEM vision equipment at lower infrastructure cost.
- Include and benefit from the latest high performance CMOS imaging technology with minimum impact on OEM equipment design by re-using existing (lower speed) interfaces.
- Optimize inspection or metrology algorithm performance while off-loading the frame grabber/PC.
- Switch between high speed and high accuracy imaging by using 1 camera where otherwise at least 2 cameras with different sensor technologies are needed.